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?2010 silicon storage technology, inc. s71220-07-eol 01/10 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. eol data sheet features: ? organized as 256k x16 ? single voltage read and write operations ? 1.65-1.95v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 5 ma (typical) ? standby current: 1 a (typical) ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? fast read access time ? 90 ns ? latched address and data ? fast erase and word-program ? sector-erase time: 36 ms (typical) ? block-erase time: 36 ms (typical) ? chip-erase time: 140 ms (typical) ? word-program time: 28 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-ball wfbga (4mm x 6mm) micro package ? 48-bump xflga (4mm x 6mm) micro package ? 48-ball xfbga z-scale package product description the SST39WF400A device is a 256k x16 cmos multi- purpose flash (mpf) manufactured with sst?s proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and ma nufacturability compared with alternate approaches. the SST39WF400A writes (pro- gram or erase) with a 1.65-1.95v power supply. this device conforms to jedec standard pin assignments for x16 memories. featuring high-performance word-program, the SST39WF400A device provides a typical word-program time of 28 sec. the device uses toggle bit or data# poll- ing to detect the completion of the program or erase opera- tion. to protect against inadver tent writes, it has on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the SST39WF400A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. for all system applications, it significantly improves performance and reliability, while lowering power consumption. it inherently uses less energy during erase and program than alternative flash technolo- gies. when programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet surface mount requirements, the SST39WF400A is offered in both a 48-ball tfbga package, 48-ball micro- packages, and a 48-ball z-scale package. see figures 2, 3, and 4 for pin assignments. 4 mbit (x16) multi-purpose flash SST39WF400A SST39WF400A1.8v 4mb (x16) mpf memory downloaded from: http:///
2 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the SST39WF400A is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 5). word-program operation the SST39WF400A is programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed within 40 s. see figures 6 and 7 for we# and ce# controlled pro- gram operation timing diagrams and figure 18 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during the internal program opera- tion are ignored. sector/block-e rase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the SST39WF400A offers both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. see figures 11 and 12 for timing waveforms. any commands issued during the sec- tor- or block-erase operation are ignored. chip-erase operation the SST39WF400A provides a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 10 for timing diagram, and figure 21 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the SST39WF400A provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 3 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 data# polling (dq 7 ) when the SST39WF400A is in the internal program oper- ation, any attempt to read dq 7 will produce the comple- ment of the true data. once the program operation is completed, dq 7 will produce true da ta. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be inva lid: valid data on the entire data bus will appear in s ubsequent successive read cycles after an interval of 1 s . during internal erase oper- ation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 19 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 9 for toggle bit timing diagram and figure 19 for a flowchart. data protection the SST39WF400A provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.0v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the SST39WF400A provides the jedec approved soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. this group of devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invali d commands will abort the device to read mode within t rc . the contents of dq 15 - dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the SST39WF400A also contains the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as software id entry command with 98h (cfi query command) to address 5555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. downloaded from: http:///
4 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 product identification the product identification mode identifies the devices as the SST39WF400A and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 13 for the software id entry and read timing diagram, and figure 20 for the software id entry command sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 15 for timing waveform, and figure 20 for a flowchart. figure 1: functional block diagram table 1: product identification table address data manufacturer?s id 0000h 00bfh device id SST39WF400A 0001h 272fh t1.0 1220 y-decoder i/o buffers and data latches 1220 b1.0 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 5 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 2: pin assignments for 48-ball tfbga figure 3: pin assignments for 48-ball wfbga and 48-bump xflga 1220 48-tfbga p01.0 SST39WF400A top view (balls facing down) 65 4 3 2 1 a b c d e f g h a13 a9 we# nc a7a3 a12 a8 ncnc a17 a4 a14a10 ncnc a6a2 a15a11 ncnc a5a1 a16 dq7dq5 dq2 dq0 a0 nc dq14dq12 dq10 dq8 ce# dq15dq13 v dd dq11 dq9 oe# v ss dq6dq4 dq3 dq1 v ss a2a1 a0 ce# v ss a4a3 a5 dq8 oe# dq0 a6a7 nc dq10 dq9dq1 a17 ncnc dq2 nc dq3 nc v dd we# dq12 ncnc nc dq13 a9 a10 a8 dq4dq5 dq14 a11a13 a12 dq11 dq6 dq15 a14a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 65 4 3 2 1 1220 48-wfbga-xflga p03_4.0 SST39WF400A downloaded from: http:///
6 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 4: pin assignments for 48-ball xfbga table 2: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address. a ms = a 17 for SST39WF400A address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 1.65-1.95v for SST39WF400A v ss ground nc no connection unconnected pins. t2.0 1220 table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.0 1220 a1 a2 a3 a4 a5 a6 a7 a17 a0 ce# v ss oe# dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq 8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 v dd v ss a16 a 8 a9 a10 a11 a12 a13 a14 a15 w e# n c n c n c n c n c n c n c n c top v ie w ( b alls facing do w n) 1220 39 w f400a-zke-p1.1 sst39 w f400a a b c d e f g h j k l m n p r t 65 4 3 2 1 downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 7 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 table 4: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55 h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 555 5h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h cfi query entry 5 5555h aah 2aaah 55h 5555h 98h software id exit 7 / cfi exit xxh f0h software id exit 7 / cfi exit 5555h aah 2aaah 55h 5555h f0h t4.0 1220 1. address format a 14 -a 0 (hex), addresses a ms- a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms = a 17 for SST39WF400A 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x for block-erase; uses a ms -a 15 address lines 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, SST39WF400A device id = 272fh, is read with a 0 = 1. 7. both software id exit operations are equivalent table 5: cfi query identification string 1 for SST39WF400A 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.0 1220 downloaded from: http:///
8 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 table 6: system interface information for SST39WF400A address data data 1bh 0016h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0020h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0005h typical time out for word-program 2 n s (2 5 = 32 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0005h typical time out for individual sector/block-erase 2 n ms (2 5 = 32 ms) 22h 0007h typical time out for chip-erase 2 n ms (2 7 = 128 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 5 = 64 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 5 = 64 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 7 = 256 ms) t6.0 1220 table 7: device geometry information for SST39WF400A address data data 27h 0013h device size = 2 n byte (13h = 19; 2 19 = 512 kbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 007fh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0000h y = 127 + 1 = 128 sectors (007fh = 127) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 0007h block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 7 + 1 = 8 blocks (0007h = 7) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.0 1220 downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 9 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to 11v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial 0c to +70c 1.65-1.95v industrial -40c to +85c 1.65-1.95v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 16 and 17 downloaded from: http:///
10 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 table 8: dc operating characteristics v dd = 1.65-1.95v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=5 mhz, v dd =v dd max read 15 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 20 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 5 2 a ce#=v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.2v dd v dd =v dd min v ih input high voltage 0.8v dd vv dd =v dd max v ol output low voltage 0.1 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.1 v i oh =-100 a, v dd =v dd min t8.2 1220 1. typical conditions for the active current shown on t he front page of the data sheet are average values at 25c (room temperature), and v dd = 1.8v. not 100% tested. 2. 5 a is the maximum i sb for all 39wf400a commercial grade devices. 20 a is the maximum i sb for all 39wf400a industrial grade devices. for all 39wf400a commerc ial and industrial devices, i sb typical is 1 a. table 9: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t9.0 1220 table 10: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 1220 table 11: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.0 1220 downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 11 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 ac characteristics table 12: read cycle timing parameters v dd = 1.70-1.95v for 90 ns 1 v dd = 1.65-1.95v for 100 ns 1. 90 ns parts will only support voltage range 1.70-1.95v. symbol parameter SST39WF400A-90 SST39WF400A-100 units min max min max t rc read cycle time 90 100 ns t ce chip enable access time 90 100 ns t aa address access time 90 100 ns t oe output enable access time 50 50 ns t clz 2 2. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 ns t olz 2 oe# low to active output 0 0 ns t chz 2 ce# high to high-z output 40 40 ns t ohz 2 oe# high to high-z output 40 40 ns t oh 2 output hold from address change 0 0 ns t12.2 1220 table 13: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 40 s t as address setup time 0 ns t ah address hold time 50 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 50 ns t wp we# pulse width 50 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 50 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 50 ms t be block-erase 50 ms t sce chip-erase 200 ms t13.0 1220 downloaded from: http:///
12 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1220 f03.1 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 17 for SST39WF400A 1220 f04.1 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 17 for SST39WF400A x can be v il or v ih, but no other value. downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 13 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 7: ce# controlled prog ram cycle timing diagram figure 8: data# polling timing diagram 1220 f05.1 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 17 for SST39WF400A x can be v il or v ih, but no other value. 1220 f06.1 address a ms-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 17 for SST39WF400A downloaded from: http:///
14 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 9: toggle bit timing diagram figure 10: we# controlled chip-erase timing diagram 1220 f07.1 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 17 for SST39WF400A 1220 f08.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-e rase operation the we# and ce# signals are interchange- able as long as minimum ti mings are met. (see table 13) a ms = most significant address a ms = a 17 for SST39WF400A x can be v il or v ih, but no other value. downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 15 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 11: we# controlled block-erase timing diagram figure 12: we# controlled sector-erase timing diagram 1220 f09.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation the we# and ce# signals are interchangeable as long as minimu m timings are met. (see table 13) a ms = most significant address a ms = a 17 for SST39WF400A x can be v il or v ih, but no other value. 1220 f10.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sect or-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 13) a ms = most significant address a ms = a 17 for SST39WF400A x can be v il or v ih, but no other value. downloaded from: http:///
16 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 13: software id entry and read figure 14: cfi query entry and read 1220 f11.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 272fh for SST39WF400A x can be v il or v ih, but no other value. 1220 f12.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value. downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 17 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 15: software id exit/cfi exit 1220 f13.1 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value. downloaded from: http:///
18 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 16: ac input/output reference waveforms figure 17: a test load example 1220 f14.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (v dd ) for a logic ?1? and v ilt (v ss ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times are (10% ? 90%) <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1220 f15.1 to tester to dut c l v dd 25k 25k downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 19 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 18: word-program algorithm 1220 f16.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value. downloaded from: http:///
20 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 19: wait options 1220 f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 21 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 20: software id/cfi command flowcharts 1220 f18.0 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation note: x can be v il or v ih , but no other value. downloaded from: http:///
22 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 21: erase command sequence 1220 f19.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value. downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 23 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 product ordering information valid combinations for SST39WF400A SST39WF400A-90-4c-b3ke SST39WF400A-90-4c-c1qe SST39WF400A-90-4c-m1qe SST39WF400A-90-4i-b3ke SST39WF400A-90-4i-c1qe SST39WF400A-90-4i-m1qe SST39WF400A-90-4i-zke 1 note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 leads or balls q = 48 balls or bumps (66 possible positions) package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) c1 = xflga (0.5mm pitch, 4mm x 6mm) m1 = wfbga (0.5mm pitch, 4mm x 6mm) z = xfbga temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 90 = 90 ns device density 400 = 4 mbit voltag e w = 1.65-1.95v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 39 wf 400a - 90 - 4c - b3k e xx x x xxx x - xxx -x x -xx x x 1. for additional xfbga, zke information contact sst sales. downloaded from: http:///
24 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 packaging diagrams figure 22: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 65 4 3 2 1 65 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05(48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm downloaded from: http:///
eol data sheet 4 mbit multi-purpose flash SST39WF400A 25 ?2010 silicon storage technology, inc. s71220-07-eol 01/10 figure 23: 48-ball very-very-thin-profile, fine -pitch ball grid array (wfbga) 4mm x 6mm sst package code: m1q figure 24: 48-bump extremely-thin-profile, fine -pitch land grid array (xflga) 4mm x 6mm sst package code: c1q l k j h g f e d c b a abcdefghjkl 65 4 3 2 1 65 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.32 0.05(48x) a1 indicator 4 6.00 0.08 2.50 5.00 a1 corner top view 48-wfbga-m1q-4x6-32mic-5 note: 1. although many dimensions are similar to those of jedec publication 95, mo-225, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no ball is present in position a1; a gold-colored indicator is present. 5. ball opening size is 0.29 mm ( 0.05 mm) 1mm detail side view seating plane 0.20 0.06 0.63 0.10 0.08 l k j h g f e d c b a abcdefghjkl 65 4 3 2 1 65 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.29 0.05(48x) a1 indicator 4 6.00 0.08 2.50 5.00 a1 corner top view 48-xflga-c1q-4x6-29mic-5 note: 1. although many dimensions are similar to those of jedec publication 95, mo-222, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no bump is present in position a1; a gold-colored indicator is present. 1mm detail side view seating plane 0.04 + 0.025/ - 0.015 0.52 max.0.473 nom. 0.08 downloaded from: http:///
26 eol data sheet 4 mbit multi-purpose flash SST39WF400A ?2010 silicon storage technology, inc. s71220-07-eol 01/10 table 14: revision history number description date 00 ? initial release mar 2003 01 ? added 90 ns speed parts ? output leakage current changed from 10 a to 1 a in table 8 on page 10 apr 2003 02 ? removed ?typical? column from table 8 on page 10 jun 2003 03 ? added 90 ns commercial temperature range mpns for all packages oct 2003 04 ? 2004 data book ? updated the b3k, m1q, and c1q package diagrams nov 2003 05 ? added footnote to max isb parameter in table 8 on page 10 jun 2004 06 ? added xfbga, zke package information to features on page 1 ? added xfbga, zke pin assignment figure 4 on page 6 ? added zke valid combinations to product ordering information ? removed 100 ns valid combinations from product ordering information ? removed pb products from valid combinations jun 2009 07 ? eol of all SST39WF400A products. replacement parts are the sst39wf400b products found in s71370. jan 2010 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com downloaded from: http:///

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